SAPON approach: A new technique for Low Power VLSI Design

Nowadays, low power VLSI is an emerging discipline where high power consumption has become a key metric in VLSI design. High power dissipation is not regarded as good when it comes to battery lifespan in the case of battery-operated applications. It alters reliability, cooling costs, and also contributes to the reduction of battery life. Switching and short circuit leakage power play a significant role in the high-frequency dynamic transition of inputs. Several standard reduction techniques exist to reduce the power consumption of circuits. In this paper, we have scrutinized the source of power consumption in static and dynamic leakage power and introduced a new technique called the SAPON (Stackly Arranged low Power ON transistor) technique to mitigate the power reduction of circuits. We have utilized various CMOS logic circuits such as INVERTER, NAND, NOR, and MUX to implement these techniques and compared their total power consumption with the standard reduction techniques. We have examined the proposed SAPON technique along with conventional, LECTOR, LCNT, and STACK ONOFIC techniques to interpret the utility of SAPON in low-power VLSI and obtained results showing that SAPON consumes low power than standard reduction techniques. These circuits are simulated in Tanner EDA Tool with Generic 250 nm transistors.