Design of ESD Protection Circuits for LNA Using 65-nm CMOS Technology

In the past couple of years, 60 GHz communications have encountered a progress to cover industrial, scientific and commercial applications. The focus of this work is to design electrostatic discharge (ESD) for 60 GHz low noise amplifier (LNA) utilizing 65-nm CMOS technology. In order to improve performance, custom designed spiral inductor working around 60 GHz frequency band has been illustrated. The circuit under test consists of a two-stage common source low noise amplifier. The proposed ESD protection circuits consisting of customized inductor offers less parasitic capacitance and renders lower RF degradation. The measured results shows that the proposed design achieves a gain of 37 dB and noise Figure of 2.745 dB at 60 GHz with 20 mW power consumption.