Time-Domain Power Distribution Network (PDN) Analysis for 3-D Integrated Circuits Based on WLP-FDTD

In this article, a new efficient unconditionally stable time-domain modeling algorithm based on the weighted Laguerre polynomial finite-difference time-domain (WLP-FDTD) method is proposed for noise analysis of complex three-dimensional (3-D) power distribution networks (PDNs) including interposers, chips, through-silicon via (TSV) arrays, bumps, and metal–insulator–metal (MIM) capacitors. Combined with weighted Laguerre polynomials (WLPs) as basis functions and Galerkin’s testing procedure, the time variables in the differential equations can be eliminated. Complex structures composed of different ON-chip/interposer PDNs and TSV/bump arrays are modeled and assembled. Subsequently, the differential equations of the 3-D PDN are derived and solved based on WLP-FDTD. Thus, the proposed algorithm can obtain the transient response and analyze noise coupling in a complex 3-D integrated circuit (IC) for the first time. Meanwhile, based on three reasonable test cases, the algorithm can save at least 99.3% and 77.0% computational time compared with the conventional FDTD and SPICE methods, respectively. In addition, the simultaneous switching noise (SSN) in a popular 3-D PDN structure is modeled, calculated, and optimized. An optimal decoupling capacitor selection scheme is discussed, and efficient SSN suppression is achieved.