Logic Compatible High-Performance Ferroelectric Transistor Memory

Silicon channel ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric and silicon channel suffers from high write voltage, limited write endurance and long read-after-write latency. This is due to early IL breakdown and mobile charge injection at the ferroelectric-IL interface. Here, we demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricated IL-free FeFETs with 28nm channel length (Lg) and 126nm width under a thermal budget < 400
⁰
C by integrating 5nm Hf
_0.5
Zr
_0.5
O
₂
(HZO) gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report a voltage memory window of 1.6V with a read current window
${I}_{\textit {LVT}}{/}{I}_{\textit {HVT}}$
of 10
⁵
, write voltage of ±1.6V with 20ns pulses, instantaneous read-after-write latency < 300ns and a record high write endurance exceeding 10
¹¹
cycles. This establishes the IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance last-level cache memory.