Analysis and Modelling of pMOS based Classical Low Drop Out Regulators: A Time Domain Perspective

A control centric analysis and design of the low drop out (LDO) voltage regulator is presented in this work. The design complexity involving interdependence of regulating loop in frequency domain and the performance parameters for voltage regulator is simplified for intuition by the development of signal flow graph (SFG). A model based on the SFG is developed and tested in Matlab/Simulink environment for a desired time and frequency domain specification. Time domain optimisation for a given steady state accuracy and settling is formulated based on the developed model.