Energy Efficient Lif Neuron Circuit Using Hybrid Cmos-Nems in 65 Nm Cmos Technology

In this paper, we show that NEMS plays a key role to reduce the leakage current for designing the sub-threshold neuromorphic circuits in 65 nm CMOS technology. For the first time, we propose a novel energy efficient hybrid CMOS-NEMS leaky integrate and fire (LIF) neuron circuit and investigate the impact of fabricated sub-50 mV NEMS on the leakage power and overall energy consumption. As per the measurement results, the sub-50-mV NEMS having a small air gap of only 100 nm exhibits very low hysteresis (<20 mV), low turn ON delay (15 ns), and low sub-threshold swing of 2 mV/decade, a maximum ON-state conductance value of 0.1 A/(V·µm) with zero leakage current. We analyze the performance of a biologically-inspired energy efficient neuron circuit in terms of leakage power consumption with biologically plausible firing rates. Our results show that the proposed CMOS-NEMS neuron circuit gives around 8% reduction in energy per spike and 65% reduction in leakage power consumption than its equivalent CMOS design with the same complexity in standard 65 nm CMOS technology.