A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is employed. As a result, the thermal noise will be the major constraint for the DAC size. In addition, a compact noise-reduction technique is proposed to alleviate the adverse impact of the input-referred comparator noise on the effective resolution. Moreover, a 2.5-V on-chip LDO, which serves as the reference generator for the ADC core, is also integrated to guarantee the reference accuracy and to suppress the supply noise. To reduce the capacitive load of the comparator and boost the comparison speed, a low fan-in SAR logic is also designed. With the proposed mismatch calibration technique and the noise-reduction technique activated, measured results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 78.8 dB and 95.4 dB, respectively. At 20 MS/s, the ADC consumes 6.8mW from its 1.2 V/3.3V supplies in total, leading to an SNDR-based Schreier FOM of 170.5 dB at Nyquist. The active area of the ADC is 450 × 540μm
²
.