In-Memory Computing exceeding 10000 TOPS/W using Ferroelectric Field Effect Transistors for EdgeAI Applications

More and more applications use deep neural networks (DNN) to execute complex tasks. Depending on the application, there are high requirements regarding latency and performance parameters, especially for edge devices (edge AI). Due to the increasing challenges regarding Moore’s Law, new approaches are required. A promising candidate for this is analog in-memory computing (AIMC). In-memory computing platforms are based on crossbar structures using resistive non-volatile memories. However, many demonstrated approaches suffer from the problems of reduced accuracy as well as reliability, large analog-todigital as well as digital-to-analog converters (ADCs/DACs), and power efficiency. The in-memory computing architecture presented in this paper is utilizing ferroelectric field effect transistors (FeFETs), which are used as a non-volatile memory cell. The crossbar-based in-memory architecture eliminates the need for any DAC and also provides high parallelism with only 3-bit ADCs. This results in lower area and power usage. The implementation of operations with binary as well as variable bit depth and power efficiencies >10000 TOPS/W are presented.