A Low-Phase Error Cascode CMOS Variable Gain Amplifier With 180° Phase Control for Phase Array Systems

A comprehensive analysis is derived to understand the mechanism of phase errors in cascode CMOS variable gain amplifiers (VGAs). According to the analysis, source–drain parasitic capacitors (
$C_{\mathrm {ds}}$
) of common gate (CG) transistors in off-region are the main causes for phase errors. An independent cascode current canceling (ICCC) VGA is proposed to relax phase errors by minimizing the effect of
$C_{\mathrm {ds}}$
within a broadband. The proposed VGA achieves a 16-dB gain control with a 1.6° phase error and a 0.2-dB gain error from 15 to 25 GHz by 40-nm CMOS technology. Owing to the cascode structure, the peak gain of the VGA is 12 dB with only one stage including input–output pads consuming 16-mW power from 1.1-V voltage. Besides, the VGA can also serve as a 180° phase shifter (PS) due to ICCC structure with a 1.5° phase error and a 0.2-dB gain error from 15 to 25 GHz. The measured −3-dB bandwidth is 5 GHz, and output 1-dB compression point (OP1dB) is over 2.5 dBm in the maximum gain state. The core area is 0.065 mm
²
excluding input–output pads.