A Novel Design of High-performance Parallel-serial Conversion Interface Based on AXI-Stream4.0

The AXI on-chip bus has high bandwidth and low latency and has been widely used in system-on-chip (SoC) design. In the field programmable gate array (FPGA) prototype verification of a large SoC, AXI needs to span multiple FPGAs to achieve system interconnection, and the number of signals required by the bus conflicts with the number of chip ports. This paper proposes a feasible link protocol improvement scheme, based on the Aurora link protocol, adding a transmission error correction control scheme, namely the Go-Back-N (GBN)-Reed-Solomon (RS) scheme. This design not only ensures the design is simple and easy to implement, but also enhances the data transmission reliability of the design. By comparing the data transmission efficiency of pure GBN and GBN-RS, it is found that when the transmission efficiency reaches 80%, pure GBN requires a SNR (signal-to-noise) of 7.8 dB, while GBN-RS is only 3.3 dB, thus effectively improving the data transmission efficiency under the low SNR. In addition, by simulating three GBN-RS schemes with different packet lengths (32 bytes, 256 bytes, and 512 bytes), it is found that a packet length of 256 bytes is the best choice among the three schemes. The RS-GBN scheme under the balance of data transmission efficiency and realization overhead.