Design Considerations for Low Spur Charge Pump in High Performance Phase Locked Loops

This paper presents the analysis and design of a low-current mismatch charge pump for a high-performance Fractional-N Phase-Locked Loop (PLL). A charge pump is one of the significant contributors of frequency spurs in Fractional-N PLL. In this paper, conventional charge pump topologies gate switched, drain switched, and source switched are studied and designed. Nonidealities associated with conventional charge pump topologies - current mismatch, Up & Down skew, and clock feedthrough are analyzed. Improved charge pump topologies are explored and designed for each case in 65nm CMOS technology to reduce the current mismatch. Improved topologies utilize the negative feedback using an operational amplifier (OPAMP) to reduce the current mismatch. DC simulations show the current mismatch reduction from 20% to less than 0.06%.