Analytical Modeling of a High-Performance Heterojunction TFET with Tunneling Area Modulation

This article proposes the analytical modeling of a prescribed new architecture of a double-gate (DG) heterojunction tunnel field-effect transistor (TFET). We have used 2D Poisson’s equation to estimate the potential distribution with the aid of conformal mapping technique to consider the elliptical fringing electric flux into the gate underlapped portions. This planar structure has many structural advantages over conventional TFETs. The parallel alignment of the gate electric field lines to the tunneling direction boosts the drain current of the device. This asserts flexibility in controlling the current of the device as per the demand by tunneling area modulation. The modeling has been done taking InAs/Si combination, but other combinations like Ge/Si can be implemented as well. Our modeling has been validated by 2D TCAD simulation data. In this article, the nature of the current and subthreshold slope of the device has been captured with varying device parameters. The fabrication complexity being lower, this device is fairly compatible with modern CMOS technology in comparison to the other heterojunction TFETs.