VLSI Implementation of A Robust Threshold-Based Earthquake Early Warning System

The earthquake-early-warning-system (EEWS) is one of the effective tools to mitigate seismic hazards in real-time. In previous studies, the product of two parameters viz. ground motion period (τ
c
) and high-pass filtered vertical displacement peak amplitude (P
d
) has been extensively used to establish threshold-based EEWS. However, the threshold-based approach by employing parameter τ
c
× P
d
suffers from error and generates false alarms for low-magnitude events data corrupted with high background noise. We have proposed a robust threshold-based methodology where noise-removal by employing adaptive filter is performed to increase the SNR of events data. Moreover, owing to the fact that τ
c
exhibits uncertainty in predicting low-magnitude events though reliably predicting high-magnitude ones, whereas P
d
can reliably predict low-magnitude events, we have used a two-step threshold-based approach, where in step I, if the estimated magnitude based on parameter P
d
does not cross the predetermined threshold value, then low-magnitude event is predicted; next in step II, if the estimated magnitude based on parameter τ
c
overshoots the threshold value, then high-magnitude event is predicted and warning is generated. In this paper, a novel VLSI architecture of the proposed two-step τ
c
and P
d
estimation unit has been presented and realized in both FPGA and ASIC platforms.