Index and Sort Algorithm Based on FPGA for Sorting Data

Sorting data is one of the most significant problems that have been debated in recent years in order to find the best algorithm for reducing the required time to perform the arrangement. As a result, a hardware accelerator is used to accelerate data processing. In this work, we propose the Index and Sort algorithm (IaSA) as a new sorting algorithm. Our IaSA Hardware architecture is implemented, synthesized, and simulated using Verilog HDL using FPGA vertex-5 series to measure the performance and scalability. The results of our implementations show that IaSA has the best execution time over other existing sorting algorithms. Our proposed algorithm shows execution time smaller than the fastest literature algorithm, odd even merge sort, by about 11.4%, 40.9%, 62.8%, and 41.1% for 4, 8, 16, and 32 dataset sizes respectively.