Enhancing ON- and OFF-State Performance of Quasi-Vertical GaN Trench MOSFETs on Sapphire With Reduced Interface Charges and a Thick Bottom Dielectric

In this letter, we report the enhancement of ON- and OFF-state performance in vertical GaN trench MOSFETs through fabrication process optimization. The ON-state device performance was effectively improved by reducing MOS channel interface charges with a piranha cleaning process prior to the gate dielectric deposition. For the OFF-state, the breakdown voltage (
${V}_{\text{BR}}$
) of the device was greatly enhanced via suppressing the electric field in the gate dielectric near the bottom of the gate trench with a thick bottom dielectric process. As a result, high-performance quasi-vertical GaN trench MOSFETs grown on sapphire substrates with a 4-
$\mu \text{m}$
-thick drift layer are demonstrated, exhibiting a low specific ON-resistance of 0.95
$\text{m}\Omega \cdot \text{cm}^{2}$
, a high maximum drain current of 3.4 kA/cm
²
, a large threshold voltage of 6.1 V (defined at
${I}_{\text{D}}$
of 1 A/cm
²
), and a high
${V}_{\text{BR}}$
of 485 V.