LaSiOx- and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high-
${k}$
/metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiO
_x
for nMOS and Al
₂
O
₃
for pMOS–at the interface between SiO
₂
and HfO
₂
as a promising approach to engineer the high-
${k}$
band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiO
_x
and Al
₂
O
₃
insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiO
_x
and Al
₂
O
₃
insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al
₂
O
₃
) or even improved carrier mobility (LaSiO
_x
) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al
₂
O
₃
layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiO
_x
(for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiO
_x
layer on top of the beneficial Al
₂
O
₃
layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle.