An FPGA Prototyping of the GIFT Cipher for Image Security Applications

Nowadays, images are frequently used for vital information sharing; therefore, its data security is of prime concern. In this work, the GIFT is implemented on an FPGA device with 256×256 and 512×512 sized gray and RGB images. Hardware prototyping of the architecture is done on the Xilinx ZCU102 platform featuring the Zynq UltraScale+ xczu9eg-2ffvb1156 FPGA. The resource usage, efficiency, throughput, and power studies are highlighted. At a maximum clock frequency of 770/530 MHz, encryption/decryption consumes 643/660 mW of power. Furthermore, statistical analyses for histogram, correlation, entropy, and key sensitivity are carried out. In this study, the average entropy of the original-to-encrypted image is enhanced to 11.38% and improved compared to previous work. The average correlation coefficient is reduced to 99.90/99.80/99.90% in the vertical/horizontal/diagonal direction.