An Implementation Method of HEVC Dataflow Graph Based on Reconfigurable Processer

Aiming at the problems of low resource utilization and long algorithm execution time caused by unreasonable task division when complex applications in high-efficiency video coding are mapped on a reconfigurable processor. This paper proposes a method for implementing a dataflow graph (DFG) of HEVC algorithm based on a reconfigurable processor. According to analyzed the data dependence and parallelism between the algorithms, the loop optimization is performed on the HEVC part with more loops and the algorithm DFG is constructed. This paper mainly analyzes the mapping of smaller-scale DFG to different processing units in the array processor. The experimental results show that compared with the serial scheme, the speedup ratio can reach up to 7.4x, the processing element utilization can be increased by up to 80%, and the execution time can be reduced by up to 86%.