Thermal Aware Floorplanner for Multi-Layer ICs with Fixed-Outline Constraints

In the deep sub-micron technology, the chip size is increasing exponentially with the increasing number of functional modules that need to be placed on the single layer. Also, the wirelength and chip temperature are increasing which degrades the performance of the chip. The Three Dimensional Integrated Circuit (3D IC) structure is found as an alternative for conventional Two-Dimensional IC (2D IC). The 3D IC has attractive features like vertical stacking of layers, and Through-Silicon-Via (TSV) interconnect which helps to reduce chip area and wirelength. But, there are few bottleneck challenges in the design phase, such as increased number of TSVs that occupies more chip area and chip temperature due to heterogeneous integration. In order to address these challenges we aim to present a three-phase multi-objective optimization algorithm based on the Genetic Algorithm (GA) and Simulated Annealing (SA) during the floorplanning stage. The three phases of the proposed algorithm are (i). Layer Assignment, (ii). Intra-layer floorplanning, (iii). Inter-layer floorplanning. The modern design metrics such as chip area, wirelength, number of vias, and chip temperature are considered for the optimization. We attained the best results in the state-of-the-art GSRC benchmark circuits, giving a maximum of 8.19% reduction in TSV count and 23.85% reduction in the chip peak temperature.