8x8 SFQ based Multiplier design using Verilog in Cadence

For any Digital Signal Processing application, designing an efficient multiplier for any filter plays a vital role. The proposed methodology is to design an efficient 8-Bit SFQ multiplier. SFQ circuits have a larger advantage than semiconductor circuits, even though semiconductor circuits require a refrigeration system. The operation speed and power dissipation are two advantages of the SFQ logic. To implement this SFR logic an efficient carry select adder is designed. Modified Booth Encoder has been used to reduce the computations. The ASIC design procedure followed using cadence for 45nm CMOS technology as well comparison has made with parameters like area, delay, power dissipation.