An ESD layout reliability verification method based on PERC

With the increasing scale of integrated circuits and the smaller process size, ESD (Electro-Static discharge) reliability verification has become an essential task in the design of SoC chips. The ESD protection circuits provide ESD current paths to avoid damage caused by electrostatic current flowing into the internal circuits of IC during ESD discharge. This paper introduces the causes, types and protection requirements of electrostatic discharge, focusing on the impact of parasitic resistance on ESD in layout and the automatic extraction of ESD parasitic resistance based on PERC tool. The verification method described in the paper can be used in inspection of the reliability of ESD layout in SOC chip.