Design and implementation of GPIO subsystem using external foundry I/O buffer

Due to business and manufacturing capacity reasons, semiconductor companies may choose to outsource fabrication, assembly or testing. In this paper, design method of the low speed I/O subsystem in the platform controller hub (PCH) comprising of both hard intellectual property (IP) and soft IP, and the evolution of the implementation leading to the final adaptation with external foundry buffer is presented. Novel techniques to map Intel analog buffer with external foundry buffer to enable direct reuse of existing GPIO Chassis controller (soft IP). The design method and implementation successfully enabled the first PCH fabricated at external foundry, with zero post silicon bugs in the low speed I/O subsystem.