A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier

Decimal computation is highly demanded in many human-centric applications such as banking, accounting, tax calculation, and currency conversion. Hence the design and implementation of radix-10 arithmetic units attract the attention of many researchers. Among the basic decimal arithmetic operations, multiplication is not only a frequent operation but also has high complexity and considerable power consumption. Therefore, this paper concentrates on this issue and studies a general design methodology that reduces power/energy consumption via localizing switching activity without compromising target performance. This method decomposes a digit multiplier into smaller ones, like Karatsuba’s algorithm, while the multiplicand and the multiplier can be partitioned into different sizes. We take advantage of various size partitions in two types of symmetric and asymmetric, which final designs provide specific characteristics. All designs were implemented using VHDL and synthesized in the Design-Compiler toolbox with TSMC 130 nm Technology file. The results are significant; in respect to the original design, by a random test vector, 25% power reduction is achieved with no effect on latency and a negligible area penalty. Moreover, the experimental results indicate a potential for considerable reduction of power dissipation based on statistical properties of possible input data.