Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFET-based STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.