Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

With CMOS technology scaling and increased short channel effects, spin-transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS-based logic-in-memory (LIM) designs consume significantly higher energy at scaled supply voltages. To enhance the energy efficiency of LIM circuit designs, this work proposes a hybrid tunnel FET (TFET)/MTJ-based digital circuit design approach at
$V_{\mathbf {DD}} = 0.3$
V. A Schmitt triggered pre-charge sense amplifier (ST-PCSA) with a strong feedback mechanism at the pull-down section is considered in TFET/MTJ-based LIM designs. The proposed LIM-MTJ designs are implemented using 20 nm TEFT technology and perpendicular anisotropy CoFeB/MgO/CoFeB MTJs. Two input and, or, xor logic gates,
$2\times1$
multiplexer, 1-bit magnetic full adder (MFA), 4-bit magnetic ripple carry adder (RCA), and a simple 1-bit magnetic arithmetic and logical unit (M-ALU) are designed, exploring the proposed ST-PCSA-based hybrid TFET/MTJ logic. The proposed ST-PCSA-based hybrid TFET/MTJ LIM designs achieve ~47.2%–55.55% lower energy consumption in comparison with the PCSA-based TFET/MTJ LIM designs. Performance benchmarking with 20 nm FinFET designs demonstrates that the proposed TFET/MTJ LIM designs achieve 11.1%–25.9% lower energy consumption when compared with equivalent FinFET/MTJ-based LIM designs.