A New Positive-Sequence Detector Phase-Locked Loop Algorithm for DC Offset Rejection

This paper put forward a novel positive sequence detector phase-locked loop (PLL) algorithm established with all-pass filters to reduce the effects of the DC components present in the input signals of the PLL. The proposed algorithm was compared with a modified version of a Double Second-Order Generalized Integrator PLL, and a Fixed-Frequency Orthogonal Signal Generator PLL, which is a recent algorithm with promising results. For comparison criteria, the three PLLs were simulated using MATLAB/Simulink® platform, processing input signals with DC offset.