Evaluation of Stacked-CNTFET Structures for High-performance Applications

The performance trade-off for FET structures with different arrangements of vertically stacked CNTs, including single columns and matrices, is investigated by 3D device simulation including known relevant physical effects such as carrier tunneling through the contact barriers, scattering transport in the channel and electrostatic screening effects. While a single tube gate-all-around (GAA) based structure provides highest drain current, it is not optimal for high-frequency applications and yields lower transistor speed compared to stacked structures with reduced gate metallization.