Yield and Scaling Improvements in Next-Generation 2.5 THz SLCFET Devices to Enable Ultra-wideband DC-110GHz Switch MMICs

This paper reports improvements in the Superlattice Castellated Field Effect Transistor (SLCFET) 10-channel device process to enable fabrication of ultra-wideband DC-110GHz Single Pole Double and Triple Throw (SPDT/SP3T) MMICs. The 10-channel SLCFET device offers higher performance, but is more difficult to fabricate. Through planarization of the device contact pads, the fabrication of the gate electrode is improved, thereby improving DC yield for the devices by more than 50%. Additionally, the planarization has enabled the scaling of the device source/drain spacing to 64% of baseline devices while maintaining a greater than 50% DC yield. The decrease in the source/drain spacing reduces on-resistance while minimally impacting the off-capacitance, leading to a higher achievable switch Figure of Merit Fco >3THz. The improved FET designs demonstrated improved insertion loss in the wideband SPDT and SP3T MMICs while showing no change in isolation. These ultra-wideband MMICs offer better insertion loss and bandwidth than is possible from other conventional technologies.