FPGA-Based Double Vectors Model Predictive Torque Control for PMSM Drives Using Maximized Parallel Implement Architecture

To reduce the computation time of double vectors model predictive torque control (DV-MPTC), the maximized parallel architecture implemented in field programmable gate array (FPGA) for the surface-mounted permanent magnet synchronous motor (SPMSM) is proposed. Double vectors, which include an active vector and a zero vector, are used during one control period to reduce steady-state current ripples. In conventional implement architecture, predictive controller and speed controller are a cascaded form. By adjusting the execution sequence of one-step compensation module and candidate vector module in the cascaded predictive controller, the maximized parallel architecture is designed. Furthermore, the parallel architecture may have the problem of disordered parameter update sequence due to the different execution steps. To ensure the orderly execution of the maximized parallel architecture, a logic trigger mechanism is designed and applied in the parallel architecture. Experimental results illustrate the effectiveness of the proposed parallel implement architecture.