Design and Implementation of a 32-bit RISC-V Core

The concepts of “Open-source software” and “Open-source hardware” are thriving in the modern society. A significant part of this effort is directed towards the provision of open-source microprocessor designs. In light of this, researchers at University of California, Berkeley developed a license-free Instruction Set Architecture called “RISC-V”, which essentially defines the vocabulary of the hardware/software interface. Some crucial aspect of an open-source hardware are its extendibility, flexibility, and comprehensibility. Most designs are often extendible and well thought-out, but they are rarely comprehensible, which negatively impacts their extendibility. The common problem is that they either lack documentation or have hastily written ones. With the project that this paper represents, the mentioned problem was tackled by designing an open-source 32-bit Synthesizable RISC-V Core with detailed documentation. The design diagrams and design choices are disclosed, making it easy-to-understand. The RISC-V core is named “Hornet Core”.