0.7 V UWB LNA for 2.1-13.2 GHz Wireless Applications using 65-nm CMOS Technology

The paper presents a wideband input matching LNA with a high gain that is able to work from 2.1 GHz to 13.2 GHz. This LNA is devised on 65 nm CMOS technology using BSIM model. It consists of three stages. In the initial stage, the basic RL circuit is implemented using biasing conditions. Here, M2 is used to enhance the gain. The first and second stages are connected with the help of a series inductor and a coupling capacitor which is able to provide maximum power transfer. The second and third stages are connected using T-network in order to boost the gain in the entire bandwidth. The input and output return losses are less than −10 dB for the desired bandwidth. The power gain of greater than 15 dB is obtained in frequency range of 2.1 GHz to 13.2 GHz. The minimum noise figure of 5.5 dB is obtained at 5 GHz. The 1-dB compression point and intercept point (IIP3) are −24.5 dBm and −10 dBm respectively. The power dissipation of proposed circuit is 2.9 mW.