Study on Paradigm of Variable Length SRAM Embedded Memory Testing

In the virtue of deep submicron technology, the design of SRAM for an embedded SoC is more complex. Further, the existing test method makes the upcoming technology designs test invalidate. This is due to the mismatching between the design complexities with the emerging technologies and test environment. This kind of battling is essential while migrating to innovative technologies or methods. This paper is focused on presenting various test methods that are emerged from the era of micron to the level of deep submicron designs. Also, to delve the pitfalls in contemporary test designs, further to find research gaps. Most of the researchers have come up with various methodologies of BIST or MBIST as a best solution for testing. This paper reports various BIST design scenarios along with the fault coverage. The crucial part in embedded memory testing is test method, fault coverage, architectural design style, in which the test latency, test accuracy, test complexity, power and area acts as important design metrics. The recent papers observed with testing paradigms using parasitic extraction method along with various march algorithms developed with new tools for diagnosis, further to analyze the faulty behavior in SRAM cores.