Vertical Cladding Layer-Based Doping-Less Tunneling Field Effect Transistor: A Novel Low-Power High-Performance Device

This article introduces a novel vertical doping-less tunnel field-effect transistor (TFET), in which instead of using metal to induce charge plasma in the source region, cladding layer is utilized to engineer the energy bands in this region. The fabrication process flow of this highly scalable TFET is presented in detail. We employ a calibrated numerical simulator to study the switching and analog/RF performance of the proposed device. Moreover, the impact of different structural parameters and parasitic phenomena, such as interface trap charges and quantum confinement, on the device performance are investigated. According to the obtained results, our transistor exhibits desirable analog and digital performance including
${I}_{ \mathrm{\scriptscriptstyle ON}} = 30.02 ~\mu \text{A}/\mu \text{m}$
,
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
ratio of
$1.57\times10$
¹¹
and
${f}_{T} = 89.31$
GHz.