Electrical characterisation of high-k materials prepared by atomic layer CVD

The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO/sub 2/ as the gate dielectric. Replacement of SiO/sub 2/ with a high dielectric constant material allows an increase in the physical oxide thickness, while maintaining a low equivalent oxide thickness (EOT) and low direct tunnelling current. The high-k gate dielectric of choice will most likely be a deposited film, which makes the replacement of SiO/sub 2/, a thermally grown layer, even more challenging. Atomic layer CVD (ALCVD/sup TM/) is a well-controlled surface saturating process using gas-solid interactions to deposit thin films. The technique results in covalent bonding between the gaseous precursors and the surface bonding sites. ALCVD/sup TM/ provides highly uniform layers and the possibility to deposit many materials, including mixed oxide layers and nano-laminates. Some of the challenges facing high-k materials include achieving a high quality Si/high-k interface, film stability and solving reliability and integration issues. In this paper, we use MOS capacitors to investigate these challenges for Al/sub 2/O/sub 3/-TiN and Al/sub 2/O/sub 3/-ZrO/sub 2/-TiN gate stacks.