Drive Mode of MEMS Rate Sensors with Software Phase Locked Loop

A specialized processing and control loop design for a highly stable Software Phase Locked Loop (SPLL) & Digital Amplitude Control Loop (DACL) for MEMS Rate Sensor is discussed. The rate sensor requires good vibration amplitude stability with resonant frequency tracking as well as start-up characteristic with pre-defined frequency response. The control loops are analyzed and simulated in MATLAB, digitally implemented in a custom designed STM32F407 processor board with inbuilt unipolar 12-bit SAR ADC and DAC. Practical test results for different SPLL implementations are compared.