Full-Custom Design of Multiplicative Inverse for AES S-BOX using 4-Transistor XOR Gate

The Multiplicative Inverse is the most intricate step involved in computation of Substitution-Box values for Private Key Encryption algorithms. It is the shared common step for encryption as well as decryption. Computing the Multiplicative Inverse of a value in Galois Field GF (p) for small numbers is an easy task which is straight away obtained from its computation tables. However, it is not convenient for higher values of p. Recent implementation of Multiplicative Inverse focuses on composite field arithmetic based approaches which uses lower order fields in its implementation. This paper presents Multiplicative Inverse design in composite field arithmetic using 4-transistor XOR gate to obtain a compact Substitution-Box module in 90 nm technology. The design requires a total of 442 transistors with average power dissipation of 3.75 watts at 0.6 supply voltage. The design shows a significant drop in transistor count by 43 % compared to previously published work.