Design and Development of VLSI Architecture for Implementing Sub-Nyquist ADC

Signals with high bandwidth are used in many communication systems. High-speed analog-to-digital converters are required when working with high-frequency signals (ADC). Proper reconstructing an analog signal at the receiver needs to be sampled as per the Shannon Nyquist theorem. However, for high-frequency signals implementing high-speed ADC devices can be a limiting factor as well as expensive. The Compressive Sensing (CS) framework is a promising area to reduce these difficulties. In CS, the signal can be sampled below the Nyquist rate. We reviewed the CS process and implemented the same in the Cadence tool for continuous-time signals in our work. Our goal is to reduce the sampling rates for high-speed ADC devices. The proposed system is very well finding its application in Bio-medical signal capturing devices and RADAR surveillance systems where continuous signal acquisitions are required.