Self-Aligned E-Mode GaN p-Channel FinFET With ION > 100 mA/mm and ION/IOFF > 10⁷

This letter demonstrates self-aligned
${p}$
-channel FinFETs based on a GaN-on-Si wafer. While the self-aligned gate process helps to achieve shortest possible source-to-drain distance to compensate for low hole mobility in GaN (~20 cm
²
/
$\text{V}\cdot \text{s}$
), the FinFET-architecture provides strong electrostatic control over the channel. Our fabricated transistors with 40 nm fin width,
$L_{SD}=120$
nm and
$L_{G}=90$
nm exhibits an
$\text{I}_{\text{ON}} \approx 140$
mA/mm,
$\text{I}_{\text{ON}}/\text{I}_{\text{OFF}}>10^{7}$
,
$V_{TH}=1$
V,
$SS=150$
mV/dec,
$g_{m,max}=14$
mS/mm and
$R_{\text{ON}}=61\,\,\Omega \cdot $
mm. By precisely controlling the recess depth, enhancement-mode (E-mode) operation was also achieved. Our best E-mode device shows an
$\text{I}_{\text{ON}} \approx 125$
mA/mm,
$\text{I}_{\text{ON}}/\text{I}_{\text{OFF}}>10^{7}$
,
$V_{TH}=-0.3$
V, and
$R_{\text{ON}}=69\,\,\Omega \cdot $
mm. In addition, record low subthreshold swing of 80 mV/dec for devices with fin width of 40 nm and
$L_{SD}=240$
nm attests to the strong gate control over the
${p}$
-channel achieved by the FinFET-architecture.