Design and Implementation of Complex Multiplier with Low Power and High Speed

The main objective of this research paper is to design architecture for 16-bit and 32-bit Complex Multiplier with low power and high speed by rectifying the problems in the existing method and to improve the speed by using the Compressor techniques. Besides, a Full Adder of Complex Multiplier is also improved to solve the problem of delay caused by memory bits. Both of two methods are combined to produce the high speed and low power multiplier circuit for higher bit length applications. This paper also presents a comparison of 16-bit, 32-bit Complex Multiplier on various performance parameters like power, delay and area. The proposed system is designed using Verilog with a 90nm technology library for education and is implemented through Verilog Compiler Simulator (VCS), Discovery Visual Environment (DVE) and Design Compiler of Synopsys. This design achieves higher performance, lower power and faster processing speed than other researches. The results show that it can be used to implement the 32-bit Complex Multiplier efficiently in many systems that require high performance.