Accelerating Side Channel Attack using Normalized Inter Class Variance

Correlation, Template, Machine Learning (ML) based attacks, etc. are well known Side Channel Attack (SCA) techniques widely used to extract the key of crypto systems. They exploit correlation between data under computation and corresponding power consumptions. In order to reduce the number of computations in key extraction, a power model free new technique is proposed to effectively compress the power traces of AES-128 running at FPGAs with the help of Normalized Inter Class Variance (NICV) values computed with publicly known information (cipher texts). This technique determines the end of encryption as Sample Index (SI) of power traces which has highest frequency for maxima of NICV values computed for lesser than all 16 bytes of cipher text. It estimates number of samples per round (NS) by subtracting two adjacent peak indexes of the power traces. Finally, it creates compressed traces by selecting 10% of NS samples around SI resulting in 98% compression. This technique has been validated by mounting Correlation Power Analysis (CPA) attack on several compressed power traces of AES algorithm running at Spartan 3E and Spartan 6 FPGAs. This will be extremely useful for Template and ML based attacks, where huge numbers of traces are required during the profiling (training) phase.