Charge Transfer Potential Barrier Model of a Pinned Photodiode in CMOS Image Sensors

An analytical model for quantifying the charge transfer potential barrier (CTPB) in pinned photodiode (PPD) CMOS image sensors (CISs) is proposed. The model shows that the height of the CTPB decreases with higher transfer gate (TG) voltage and lighter P-type doping concentration. Based on the thermionic emission theory and the TG surface potential characterization, the potential barrier height dependence on the pinning voltage and the TG design parameters is analyzed. The model was verified with technology computer-aided design (TCAD) simulations and the test devices were fabricated in a
$0.11 ~\mu \text{m}$
CIS dedicated process. The simulation and measurement results exhibit pretty good consistency with the proposed model.