Testing Multiple High-Speed Channels using Automated Test Equipment (ATE), SOC 93K, in parallel

High Bandwidth Memory (HBM) requires high speed data transfer between IO chips and IO to Memory stacks mounted on an interposer. KGD HBM stacks and IO chips from different vendors are mounted on high data rate/bandwidth interposer. In a multichiplet device packaging process, moving tests from final test, to be done at wafer level entails high equipment cost [4] such as prober, probecard, but has lower scrap cost. Lower scrap cost means higher yield, with respect to the current packaging technologies such as 2.5D/3D and Chiplets. Once a KGD is mounted on the interposer (and substrate) it cannot be removed if the interposer is tested faulty, wasting full package [4]. This paper discusses test methodology to test high speed data rate interconnections on the interposer prior to mounting the KGD HBM, IO chips and other chips (see Fig 1 below). High end DSO(Digital Storage Oscilloscopes) can test from 1 to 4 channels with relative ease. However, when the number of channels is in groups of 8,16-bit bus etc, using an ATE becomes more advantageous. One of the major advantages is, ATE can test multiple channels simultaneously, hence testing multiple channels becomes more feasible using an ATE. The different channels results can be overlaid on a single plot. The final overlay plot provides important information on which channel output is affecting the overall performance of the high-speed bus. Eye diagram [2] is an important signal integrity test to understand the quality of the communication channel in a digital system, the eye diagram provides information on the quality of the transmission line and the bandwidth of the channels. This paper discusses how an ATE could be effectively used to construct an eye diagram using shmoo plot feature of an ATE, appropriately termed Eye Diagram shmoo plot. Furthermore, as ATE can test multiple channels simultaneously, it speeds up testing on a large scale, such as testing an entire wafer. The test methodology developed herewith is a part of a fine pitch high speed channel project, where a wafer test was built with 24 high speed channels to emulate a HBM (High Bandwidth Memory) application with a bump pitch of 55um, to demonstrate the fine pitch [3] probing and functionality using ATE. For the 24 channels simultaneously tested the result showed that 2 traces had smaller eye-width and eye-height compared to the rest of the traces, however the focus of this paper are not those results but rather how the eye diagram was implemented in the ATElevel testing. The current setup uses an Advantest 93K tester coupled with a 12” Tel prober. The ATE consists of 3x PS1600 cards with a max data rate of 1.6Gbps. For higher data rates upto 9G, PS9G card can be used. With the PS1600 card, we were able to test upto 1Gbps and eye diagram plotted for all 24 traces. A fine pitch,55um, probe card was built with 24 HBW channels, to test the HBM wafer and validate the test methodology. Fig 1. below shows an eye diagram plotted for one of the channels, P9, using shmoo plot. The basic parameters such as eye width and height can be extracted from the shmoo [1] plot shown herewith.