Fabrication Process Flow of Antenna-in-Package Fan-out Wafer Level Packaging

In this paper, the fabrication process flow and results of Antenna-in-Package through fan-out wafer level packaging process were presented. This package at size 8.5mmx8.5mmx0.35mm, consists of three redistribution layers (RDL), two mold-compound layers (M.C) and 100μm height of through mold via (TMV) interconnects. The RF functional chips were flip-chip embedded into M.C, with dielectric and Cu metal RDL routing the interconnection, slot-patch antenna which built on top of the 2
^nd
molded compound was fabricated using the IME fan-out process technology. This paper demonstrated using mold-first fan-out packaging process approach to build RDL layers on RF functional chip. In addition, the opposite side of RDL was built and connected with the front side RDL through TMV interconnects. The second molding was used for TMV filling and act as dielectric layer to build antenna on top. Several process challenges and the solutions was discussed in this paper. Key process parameters were developed and optimized to meet the critical dimensions’ specifications, good thickness uniformity and low wafer warpage conditions.