Digital Low-Dropout Regulator Design Methodology for Performance Assessment in Early Stages of Integrated Circuit Design

This paper presents a generalized digital low-dropout regulator (DLDO) modeling technique that can be adapted to various commonly seen DLDO architectures. With such a technique, a DLDO design methodology is developed to enable performance assessment in the early stages of integrated circuit design, thereby reducing the time required to make late-stage design changes, which would otherwise be extremely time-consuming. Using an actual DLDO design as a test case, experimental results show that the performance predicted by the proposed model is highly consistent with the post-layout simulations.