Modeling of Hot Carrier Injection on Gate-Induced Drain Leakage in PDSOI nMOSFET

In this paper, the gate-induced drain leakage (GIDL) current in partial depleted silicon on insulator nMOSFET was measured under different hot carrier injection conditions. With the increase of stress time, the GIDL current increases steeply under channel hot carrier condition due to the dominant electron injection into oxide and the consequent generation of interface traps. On the other hand, under the drain avalanche hot carrier condition, the additional hole injection partially cancels with the electrons, leading to a mild increase of GIDL current. By taking into account the interface traps induced threshold voltage shift, we further proposed a modified model to fit the experimental data.