A parametric model for a high speed heterogeneous current-steering digital-to-analog converter based on compiled Verilog-A and SPICE

This paper proposes an innovative modeling methodology and design flow for a heterogeneous DAC based on Verilog-A and spice, in which the parametric model of both analog and digital parts can be configured to describe the ports width and the other variables of the mixed signal circuits which are derived from the measured datas. The model is further verified by a 4 Gb/s, 14-bit heterogeneous DAC, which shows a good fitting between measured and simulated results of a variety of parameters including: gain / bandwidth, spurious-free dynamic range (SFDR) and effective number of bits (ENOB) with the input sample frequency range between 0.2 GHz and 1.5 GHz. The validation of the DAC model offers a much convenient system level simulation for heterogeneous integration and mixed signal microsystems.