Abstract:
We designed a FPGA based LDPC Decoder for decoding Type-I QC-LDPC codes with flexible code rate and code length, by which the channel adaptation could be realized with ve...Show MoreMetadata
Abstract:
We designed a FPGA based LDPC Decoder for decoding Type-I QC-LDPC codes with flexible code rate and code length, by which the channel adaptation could be realized with very fine granularity. In addition, the decoder shows good bit error rate (BER) performance whose performance loss is only O.6dB at the BER of 10−6, compared with the theoretical performance when decoding the same LDPC codes using normalized Min-Sum based layered decoding algorithm.
Date of Conference: 13-16 October 2021
Date Added to IEEE Xplore: 04 January 2022
ISBN Information: