Hardware Implementation of CNN Based on FPGA for EEG Signal Patterns Recognition

CNNs are becoming increasingly used in deep learning applications, such as image classification, speech recognition, and medicine, to mention a few. CNN inference, on the other hand, is computationally costly. Traditional CPU and GPU-based neural network platforms have disadvantages of large size and high energy consumption, which make it difficult to deploy in industrial production sites. This work proposes a Software design automation CNN inference hardware accelerator. The aim is to speedup inference calculation and easy-to-use for light weight CNN. The design is implemented in the PYNQ-Z2 development board, which is based on the Xilinx Zynq-7000 System on Chip (SoC). The Proposed Framework consumes fewer logical resources on the FPGA while performing network functions rapidly and accurately. In addition, the proposed scheme is evaluated in terms of resource consumption and performance against that of other researchers.