Innovative Power Integrity Analysis and Post-Silicon Co-relation for HSIOs

In today’s world as the High-Speed IO (HSIO) data rate is rapidly increasing, meeting the Power Integrity specifications at the die, and doing post silicon correlation & comparing with pre-silicon simulation result has become more challenging. As we try to reduce time to market, maintaining high quality & confidence in the IP (Intellectual Property) which caters multiple product segment has become absolute necessary. The post silicon correlation will also provide a very high confidence on the silicon process node and its learning & improvement for future process node development. Power supply noise specification for HSIO has been scaling to meet PSIJ (Power Supply Induced Jitter) and adds more complexity to the solutions and correlation data gives more confidence in the methodology used for pre-silicon simulation & remove unnecessary pessimism in the design which helps to reduce BOM (Bill of Material) cost & adoption for future generation IPs. This paper deals with accurate methodology and analysis on the various levels of PDN (Power Delivery Network) & co-relation of silicon data looking towards die, package, board so that the IP qualifies noise spec and reusability across multiple product segment thus improving predictability & quality of IP.