A Layout Optimization Method to Reduce Commutation Inductance of Multi-Chip Power Module Based on Genetic Algorithm

This paper describes an automatic optimization method for multi-chip power module (MCPM) layout based on template generation and evolutionary computation techniques. The method is developed with particular emphasis on reducing the commutation inductance and balancing the branch inductances among paralleled chips of the module. An automatic layout generation from netlist and design constraints to ready-to-fabricate prototype is carried using two-step graph-based template generation and genetic algorithm-based sizing approach. The method employs the built-in multi-port discrete circuit model for fast evaluation of layout inductance for parasitics extraction. An analytical model is also established to assist the design of embedded snubber in the post-process stage. The layout design of a 4-chip SiC module is demonstrated. Both the simulations and the experiments are conducted to illustrate the advantage of performing the automatic optimization from the initial stage of the design process.